Nowadays, to increase integration and lower power consumption of a semiconductor device, a plurality of LSIs having different power supply voltages are connected to one another, and circuits having different power supply voltages are laid out on the same chip. Thus, a tolerant input/output circuit is used in such a semiconductor device. A tolerant input/output circuit operates with no difficulty even when inputting an input signal having a voltage higher than a power supply voltage. In such a tolerant input/output circuit, it is required that power consumption be reduced and operation frequency be improved.
FIG. 1 illustrates a tolerant input/output circuit of a first conventional example. The tolerant input/output circuit enters an output mode when an enable signal En has an L level. In the output mode, either one of output transistors P1 and N1 is activated in response to data Do. This provides an output signal, which is in phase with the data Do, from an input/output terminal Tio to an external circuit (not illustrated). The tolerant input/output circuit enters an input mode when the enable signal En has an H level. In the input mode, the output transistors P1 and N1 are both inactivated, and an input signal Di provided from the external circuit to an input/output terminal Tio is further provided to an internal circuit.
To reduce power consumption, when the tolerant input/output circuit is in a standby state, the supply of power supply voltage VDD is suspended regardless of the state of the external circuit connected to the input/output terminal Tio.
The P-channel MOS transistor P2 is activated in a situation in which the tolerant input/output circuit is in the standby state, the supply of power supply voltage VDD (3.3 V) is suspended, and input signal VIH (5 V) having a voltage higher than the power supply voltage VDD is input to the input/output terminal Tio as the input signal Di. In response to activation of the P-channel MOS transistor P2, the input signal VIH is applied to the gate of the output transistor P1, which is formed by a P-channel MOS transistor. Accordingly, the output transistor P1 is not activated, and a current path from the input/output terminal Tio to the source of the power supply voltage VDD is not formed. That is, the input/output terminal Tio does not receive the power supply voltage VDD.
In the above-mentioned situation, a P-channel MOS transistor P3, which is included in a transfer gate 1, is activated. Activation of the transistor P3 applies the input signal VIH to the gate of a P-channel MOS transistor P4, which is included in a transfer gate 2. As a result, the P-channel MOS transistor P4 and an N-channel MOS transistor N2, which are included in a transfer gate 2, are both inactivated. Therefore, a current path connecting the input/output terminal Tio, the transistor P2, the transfer gate 2, and an NAND circuit 3 is not formed.
A back gate control circuit 4 supplies an N-well (back gate) of the transistors P1 to P4 with voltage having a level that is greater than or equal to the power supply voltage VDD even if the supply of power supply voltage VDD is suspended. This prevents the generation of a PN junction diode between the power supply voltage VDD and the N-well of the transistors P1 to P4.
Therefore, in a state in which the supply of the power supply voltage VDD is suspended, the formation of unnecessary current paths is prevented even if a high voltage input signal VIH is input to the input/output terminal Tio. In this manner, power consumption is reduced in the tolerant input/output circuit of FIG. 1.
The tolerant input/output circuit enters the input mode when the power supply voltage VDD is supplied and the enable signal En has an H level. In the input mode, when the input/output terminal Tio is provided with the input signal VIH having a voltage higher than the power supply voltage VDD by an amount that is greater than or equal to the threshold value of a P-channel MOS transistor, the transistor P2 is activated and the input signal VIH is applied to the gate of the output transistor P1. This inactivates the output transistor P1. Thus, a current path connecting the input/output terminal Tio, the output transistor P1, and the source of the power supply voltage VDD is not formed.
In this situation, the transistor P3 of the transfer gate 1 is activated, the input signal VIH is applied to the gate of the transistor P4 of the transfer gate 2, and the transistor P4 is inactivated. As a result, only the N-channel MOS transistor N2 is activated in the transfer gate 2, and voltage that is lower than the power supply voltage VDD by an amount corresponding to the threshold value of the transistor N2 is applied to the output terminal of the NAND circuit 3.
At this point of time, the enable signal En has an H level, and the output signal of the NAND circuit 3 has an H level, or the power supply voltage VDD level. Therefore, a current path connecting the input/output terminal Tio, the transistors P2 and N2, and the NAND circuit 3 is not formed.
Furthermore, in the input mode, the N-channel MOS transistor N3 is inactivated in response to the enable signal En having an H level. Thus, a current path connecting the input/output terminal Tio, the transfer gate 1, the transistor N3, and the ground GND is not formed. Japanese Patent No. 3557694 describes a structure similar to the input/output circuit of FIG. 1.
FIG. 2 illustrates a tolerant input/output circuit of a second conventional example described in Japanese Patent No. 3190233. In this tolerant input/output circuit, when the enable signal En has an H level, either one of the output transistors P5 and N4 is activated in accordance with the data Do, and an output signal that is in phase with the data Do is output from the input/output terminal Tio. When the enable signal En has an L level, the output transistors P5 and N4 are both inactivated, and the input signal DI provided from an external circuit to the input/output terminal Tio is further provided to an internal circuit.
To reduce power consumption, when the tolerant input/output circuit is in a standby state, the supply of power supply voltage VDD is suspended regardless of the state of the external circuit connected to the input/output terminal Tio.
When the tolerant input/output circuit is in the standby state and the supply of power supply voltage VDD (3.3 V) is suspended, if a high voltage input signal V-H is input to the input/output terminal Tio as the input signal Di, the P-channel MOS transistor P6 is activated, and the input signal VIH (5 V) is applied to the gate of the output transistor P5. However, the output transistor P5 is inactivated in this state. Thus, a current path from the input/output terminal Tio to the source of the power supply voltage VDD is not formed.
Furthermore, the P-channel MOS transistor P7 is activated, and the input signal VIH is applied to the gate of the P-channel MOS transistor P8. Thus, the transistor PC is inactivated. Accordingly, a current path connecting the input/output terminal Tio, the transistors P6, P8, and P9, and the source of the power supply voltage VDD is not formed.
In addition, the P-channel MOS transistors P10 and P11 are inactivated. Thus, the N-well of each of the transistors P5, P6, and P8 is in an indefinite state. This prevents the formation of a PN junction diode between the power supply voltage VDD and the N-well of the transistors P5, P6, and P8.
Similar operations are performed when the tolerant input/output circuit is in the input mode, supplied with the power supply voltage VDD, and receives the enable signal En at an L level even if a high voltage input signal VIH is input to the input/output terminal Tio.
A pull-down resistor R1 is connected between the transistor N6 and the ground GND. When the tolerant input/output circuit shifts from the input mode to the output mode, the pull-down resistor R1 lowers the gate voltages of the transistors P8 and P′11 to the ground GND level. This quickly activates the transistors P8 and P11 and enables stable shifting to the output mode.
FIG. 3 illustrates a tolerant input/output circuit of a third conventional example described in Japanese Patent No. 3441238. The tolerant input/output circuit drives output transistors P12 and N5 in accordance with a plurality of input signals IN1 to INN.
The P-channel MOS transistor P13 is activated in a situation in which the tolerant input/output circuit is in the standby state, the supply of power supply voltage VDD is suspended, and a high voltage input signal VIH is input to the input/output terminal Tio. In response to activation of the P-channel MOS transistor P13, the input signal VIH is applied to the gate of the output transistor P12. However, the output transistor P12 is not activated in this state. Thus, a current path connecting the input/output terminal Tio, the output transistor P12, and the source of the power supply voltage VDD is not formed.
Furthermore, the P-channel MOS transistor P14 is activated, and the input signal VIH is applied to the gate of the P-channel MOS transistor P15. Thus, the transistor P15 is inactivated. Accordingly, a current path connecting the input/output terminal Tio, the transistors P13 and P15, and the source of the power supply voltage VDD is not formed.
Moreover, the P-channel MOS transistor P16 is activated, and the input signal VIH is applied to the N-well of the transistors P12, P13, P14, P15, P16, and P17. This prevents the formation of a PN junction diode between the power supply voltage VDD and the N-well of each transistor P12, P13, P14, P15, P16, and P17.
The pull-down resistor R1 is connected between the transistor N6 and the ground GND. When the tolerant input/output circuit shifts from the input mode to the output mode, the pull-down resistor R1 lowers the gate voltages of the transistors P8 and P11 to the ground GND level. This quickly activates the transistors P8 and P11 and enables stable shifting to the output mode.
FIG. 4 illustrates a fourth conventional example of a tolerant input/output circuit that enters the output mode when the enable signal En has an L level. In the output mode, either one of output transistors P12 and N7 is activated based on data Do, and an output signal, which is in phase with the data Do, is output from an input/output terminal Tio. The tolerant input output circuit enters the input mode when the enable signal En has an H level. In the input mode, the output transistors P12 and N7 are both inactivated, and an input signal Di input to the input/output terminal Tio from an external device is provided to an internal circuit.
When an input signal VIH having a voltage of 5 V, which is higher than the power supply voltage VDD by an amount that is greater than or equal to the threshold value of a P-channel MOS transistor, is input to the input/output terminal Tio, a transistor P13 is activated, and the input signal VIH is input to the gate of an output transistor P12.
As a result, the output transistor P12 is inactivated. Thus, a current path is not formed from the input/output terminal Tio to the power supply voltage VDD via the output transistor P12.
A transistor P14 is also activated, and a node N1 shifts to the input signal VIH level. This inactivates a transistor P15. Thus, current path is not formed from the input/output terminal Tio to the power supply voltage VDD through the transistors P13, P15, and P16.
The back gates of the output transistor P12 and the transistors P13 to P15 are clamped at the input signal VIH level by a back gate control circuit 5. This prevents formation of PN junction diode between the source power supply voltage VDD and the N-well of the transistors P12 to P15.
If a signal having the same level as the power supply voltage VDD is input to the input/output terminal Tio when the tolerant input/output circuit is supplied with power supply voltage VDD and selected in the input mode, the transistors P13 and P14 are inactivated, and the node N1 is shifted to the ground GND level by a pull-down resistor R2. The pull-down resistor R2 is arranged to pull down the node N1 to the ground GND level when a signal having the same level as the power supply voltage VDD is input to the input/output terminal Tio.
When the node N1 shifts to the GND level, the transistor P15 is activated and the transistor P16 is activated. Thus, the gate of the output transistor P12 shifts to the power supply voltage VDD level and the output transistor P12 is inactivated. Further, an output transistor N7 is also inactivated. Accordingly, the input/output circuit operates in the same manner as a normal CMOS input/output circuit, and the input signal Di is provided to the internal circuit.